3/8

ST 486 DX ASIC CORE

®

SYSTEM MANAGEMENT MODE

System Management Mode (SMM) provides an

additional interrupt and a separate address space

that can be used for system power management

or

software

transparent

emulation

of

I/O

peripherals.

SMM is entered using the System

Management

Interrupt

(SMI#)

or

SMINT

instruction.

While running in isolated SMM

address space, the SMI interrupt routine can

execute without interfering with the operating

system or application programs.

After entering SMM, portions of the CPU state are

automatically saved. Program execution begins at

the base of SMM address space.

The location

and size of the SMM memory are programmable

within the ST486DX Core. Eight SMM instructions

have been added to the 486 instruction set that

permit software entry into SMM, as well as saving

and restoring the total CPU state when in SMM

mode.

POWER MANAGEMENT

The ST486DX Core power management features

allow for a dramatic improvement in battery life

over

systems

designed

with

non-static

486

processors.

During suspend mode the typical

current consumption is less than 1 percent of the

full operation current.

Suspend mode is entered by either a hardware or

a software initiated action.

Using the hardware

method to initiate suspend mode involves a two-

pin handshake between the SUSP# and SUSPA#

signals. The software can initiate suspend mode

through the execution of the HALT instruction.

Once in suspend mode, the ST486DX Core power

consumption is further reduced by stopping the

external clock input. The resulting current draw is

typically 450 µA.

Since the ST486DX Core is

static, no internal data is lost when the clock is

stopped.

SIGNAL SUMMARY

The ST486DX Core signal set includes ten cache

interface signals, two capriciousness interface

signals, two power management signals, two

system management mode signals, one power

supply voltage control signal and one clock

multiplier control signal.

LIBRARY

The following section details the elements which

make up the ST486DX core HCMOS6 library. The

elements are organised into three categories:

- Macrocell & Macrofunctions

- Module generators

- Embedded Functions

MACROCELLS AND MACROFUNCTIONS

The HCMOS 6 library has internal macrocells that

are robust in variety and performance. The cell

selection has been driven by the need of synthesis

and HDL based design techniques. This offering is

rich in buffers, complex combinatorial cells and

multi power drive cells, which allow the synthesis

tool to create a netlist compatible with the

requirements of Place and Route tools.

Macrofunctions are implemented at layout by

utilizing macrocells and interconnecting to create

the logic function. The Macrofunctions include all

the blocks needed to build a full PC chipset sub-

system.

Examples include DRAM controller, UART, DMA

controller, Interrupt Controller, Interval Timer, IDE

Controller, RTC, PCI Controller, MIDI port, etc.

MODULE GENERATORS

A series of module generators are available to

support a range of megafunctions. These modules

enable

the

designer

to

choose

individual

parameters in order to create a compiled cell,

which meets the specific application requirements.

Generators are available for megafunctions such

as single port RAM and dual port RAM and ROM.

The compiled cell generators construct custom

cells, which are implemented using a special leaf

cell technique, ensuring predictable layout and

accurate module characteristics.

In choosing megafunctions the designer can

consider the trade-offs between speed and area to

generate a fully customized cell which meets their

specific device requirements.

EMBEDDED FUNCTIONS

Embedded

megacells

allow

access

to

technologies that have been hitherto the domain of

standard products.