GS82032T-4 datasheet(7/23 Pages) ETC1

номер детали	GS82032T-4

подробное описание детали	64K x 32 2M Synchronous Burst SRAM

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7 / 23 page

Rev: 1.04 2/2001

7/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS82032T/Q-150/138/133/117/100/66

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CR

CW

X

W

R

W

R

X

CR

R

CW

CR

Simplified State Diagram

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control

inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

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