TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT

TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

TPS771XX

FB/SENSE

1

I

Feedback input voltage for adjustable device (sense input for fixed options)

RESET

2

O

Reset output

EN

3

I

Enable input

GND

4

Regulator ground

IN

5, 6

I

Input voltage

OUT

7, 8

O

Regulated output voltage

TPS772XX

FB/SENSE

1

I

Feedback input voltage for adjustable device (sense input for fixed options)

PG

2

O

Power good

EN

3

I

Enable input

GND

4

Regulator ground

IN

5, 6

I

Input voltage

OUT

7, 8

O

Regulated output voltage

TPS771xx RESET timing diagram

† Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for

semiconductor symbology.

VI

Vres†

t

t

t

VO

Threshold

Voltage

RESET

Output

220 ms

Delay

220 ms

Delay

Output

Undefined

Output

Undefined

VIT +‡

VIT –‡

VIT –‡

VIT +‡

‡ VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.

Vres†