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STK10C68-L25 датащит (Datasheet) 9 Page - List of Unclassifed Manufacturers

№ деталь STK10C68-L25
подробность  8K X 8 nvSRAM QuantumTrap CMOS Nonvolatile Static RAM
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производитель  ETC1 [List of Unclassifed Manufacturers]
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STK10C68
September 2003
9
Document Control # ML0006 rev 0.1
If the STK10C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
CC or between E and system VCC.
HARDWARE PROTECT
The STK10C68 offers two levels of protection to
suppress inadvertent STORE cycles. If the control
signals (E, G, W and NE) remain in the STORE con-
dition at the end of a STORE cycle, a second STORE
cycle will not be started. The STORE (or RECALL)
will be initiated only after a transition on any one of
these signals to the required state. In addition to
multi-trigger protection, STOREs are inhibited when
V
CC is below 4.0V, protecting against inadvertent
STORE
s.
LOW AVERAGE ACTIVE POWER
The STK10C68 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between I
CC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, V
CC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE
cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK10C68 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the V
CC level; and 7) I/O loading.
Figure 2: I
CC (max) Reads
0
20
40
60
80
100
50
100
150
200
Cycle Time (ns)
TTL
CMOS
Figure 3: I
CC (max) Writes
0
20
40
60
80
100
50
100
150
200
Cycle Time (ns)
TTL
CMOS




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