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STK10C68-CF45 датащит (Datasheet) 7 Page - List of Unclassifed Manufacturers

№ деталь STK10C68-CF45
подробность  8K X 8 nvSRAM QuantumTrap CMOS Nonvolatile Static RAM
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производитель  ETC1 [List of Unclassifed Manufacturers]
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STK10C68
September 2003
7
Document Control # ML0006 rev 0.1
RECALL CYCLES #1, #2 & #3
(VCC = 5.0V ± 10%)
Note p: Measured with W and NE both high, and G and E low.
Note q: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate
the RECALL initiation cycle.
Note r:
If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL.
RECALL CYCLE #1: NE Controlledo
RECALL CYCLE #2: E Controlledo
RECALL CYCLE #3: G Controlledo, r
NO.
SYMBOLS
PARAMETER
MIN
MAX
UNITS
#1
#2
#3
33
tNLQXp
tELQXR
tGLQXR
RECALL Cycle Time
20
µs
34
tNLNH
q
tELNHR
tGLNH
RECALL Initiation Cycle Time
20
ns
35
tNLEL
tNLGL
NE Set-up
0
ns
36
tGLNL
tGLEL
Output Enable Set-up
0
ns
37
tWHNL
tWHEL
tWHGL
Write Enable Set-up
0
ns
38
tELNL
tGLEL
tELGL
Chip Enable Set-up
0
ns
39
tNLQZ
NE Fall to Outputs Inactive
20
ns
40
tRESTORE
Power-up RECALL Duration
550
µs
NE
G
W
E
DQ (DATA OUT)
HIGH IMPEDANCE
34
tNLNH
36
tGLNL
37
tWHNL
38
tELNL
39
tNLQZ
33
tNLQX
NE
G
W
E
DQ (DATA OUT)
HIGH IMPEDANCE
35
tNLEL
36
tGLEL
37
tWHEL
34
tELNHR
33
tELQXR
NE
G
W
E
DQ (DATA OUT)
HIGH IMPEDANCE
35
tNLGL
33
tGLQXR
34
tGLNH
37
tWHGL
38
tELGL




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