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KMM372F883BS датащи(PDF) 6 Page - Samsung semiconductor |
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KMM372F883BS датащи(HTML) 6 Page - Samsung semiconductor |
6 / 20 page DRAM MODULE KMM372F80(8)3BK/BS NOTES An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref- erence levels for measuring timing of input signals. Transi- tion times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. Measured with a load equivalent to 1 TTL loads and 100pF. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. Assumes tha tRCD ≥tRCD(max). This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operat- ing parameter. They are included in the data sheet as electri- cal characteristics only. If tWCS ≥tWCS(min) the cycle is an early write cycle and the data out pin will remain high imped- ance for the duration of the cycle. If tRWD ≥tRWD(min), tCWD ≥tCWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to the CAS leading edge in early write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going , the open circuit condition of the output is achieved by RAS going. tASC ≥ 6ns. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 12. 13. 11. |
Аналогичный номер детали - KMM372F883BS |
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Аналогичное описание - KMM372F883BS |
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