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ADC08D1500CIYB датащи(PDF) 11 Page - National Semiconductor (TI) |
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ADC08D1500CIYB датащи(HTML) 11 Page - National Semiconductor (TI) |
11 / 33 page Converter Electrical Characteristics (Continued) NOTE: This product is currently in development and the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. The following specifications apply after calibration for V A =VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P,CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f CLK = 1.5 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non- Extended Control Mode, SDR Mode, R EXT = 3300 Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for T A =TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) AC ELECTRICAL CHARACTERISTICS f CLK1 Maximum Input Clock Frequency Normal Mode (non DES) or DES Mode 1.7 1.5 GHz (min) f CLK2 Minimum Input Clock Frequency Normal Mode (non DES) 200 MHz f CLK2 Minimum Input Clock Frequency DES Mode 500 MHz Input Clock Duty Cycle 200 MHz ≤ Input clock frequency ≤ 1.5 GHz (Normal Mode) (Note 12) 50 20 80 % (min) % (max) Input Clock Duty Cycle 500MHz ≤ Input clock frequency ≤ 1.5 GHz (DES Mode) (Note 12) 50 20 80 % (min) % (max) t CL Input Clock Low Time (Note 11) 333 133 ps (min) t CH Input Clock High Time (Note 11) 333 133 ps (min) DCLK Duty Cycle (Note 11) 50 45 55 % (min) % (max) t RS Reset Setup Time (Note 11) 150 ps t RH Reset Hold Time (Note 11) 250 ps t SD Syncronizing Edge to DCLK Output Delay f CLKIN = 1.5 GHz f CLKIN = 200 MHz 3.53 3.85 ns t RPW Reset Pulse Width (Note 11) 4 Clock Cycles (min) t LHT Differential Low to High Transition Time 10% to 90%, C L = 2.5 pF 250 ps t HLT Differential High to Low Transition Time 10% to 90%, C L = 2.5 pF 250 ps t OSK DCLK to Data Output Skew 50% of DCLK transition to 50% of Data transition, SDR Mode and DDR Mode, 0˚ DCLK (Note 11) ±50 ps (max) t SU Data to DCLK Set-Up Time DDR Mode, 90˚ DCLK (Note 11) 667 ps t H DCLK to Data Hold Time DDR Mode, 90˚ DCLK (Note 11) 667 ps t AD Sampling (Aperture) Delay Input CLK+ Fall to Acquisition of Data 1.3 ns t AJ Aperture Jitter 0.4 ps rms t OD Input Clock to Data Output Delay (in addition to Pipeline Delay) 50% of Input Clock transition to 50% of Data transition 3.1 ns Pipeline Delay (Latency) (Notes 11, 14) DI Outputs 13 Input Clock Cycles DId Outputs 14 DQ Outputs Normal Mode 13 DES Mode 13.5 DQd Outputs Normal Mode 14 DES Mode 14.5 Over Range Recovery Time Differential V IN step from ±1.2V to 0V to get accurate conversion 1 Input Clock Cycle www.national.com 11 |
Аналогичный номер детали - ADC08D1500CIYB |
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Аналогичное описание - ADC08D1500CIYB |
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