F

F

VCCO

NC

D4a

D4b

D3a

LOGIC DIAGRAM

D3b

D2a

D2b

VEE

D1a

D1b

D0a

26

27

28

2

3

4

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

5

6

7

8

9

10

Q4

Q4

VCC

Q3

Q3

Q2

Q2

D0b VCCO Q0

Q0

Q1

Q1 VCCO

D0a

D0b

D1a

D1b

D2a

D2b

D3a

D3b

D4a

D4b

F

F

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

Q4

Q4

1

* All VCC and VCCO pins are tied together on the die.

Pinout: 28-Lead PLCC (Top View)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–1

REV 2

12/93

Quint 2Input AND/NAND Gate

The MC10E/100E104 is a quint 2-input AND/NAND gate. The function

output F is the OR of all five AND gate outputs, while F is the NOR. The Q

outputs need not be terminated if only the F outputs are to be used.

PIN NAMES

Pin

Function

D0a – D4b

Data Inputs

Q0 – Q4

AND Outputs

Q0 – Q4

NAND Outputs

F

OR Output

F

NOR Output

FUNCTION OUTPUTS

F =

(D0a • D0b) + (D1a • D1b) + (D2a • D2b) +

(D3a • D3b) + (D4a • D4b)

MC10E104

MC100E104

QUINT 2-INPUT

AND/NAND GATE

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02