 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
THGBMHG6C1LBAIL датащи(PDF) 21 Page - Toshiba Semiconductor |
|
||||||||||||||||||||||||||||||
THGBMHG6C1LBAIL датащи(HTML) 21 Page - Toshiba Semiconductor |
|
|
21 / 33 page  THGBMHG6C1LBAIL 21 Jul. 31th, 2015 Input DAT (referenced to CLK-DDR mode) Input set-up time tISUddr 2.5 ns CL ≤ 20pF Input hold time tIHddr 2.5 ns CL ≤ 20pF Output DAT (referenced to CLK-DDR mode) Output delay time during data transfer tODLYddr 1.5 7 ns CL ≤ 20pF Signal rise time (all signals) (2) tRISE 2 ns CL ≤ 20pF Signal fall time (all signals) tFALL 2 ns CL ≤ 20pF 1) CLK timing is measured at 50% of VCCQ. 2) Inputs DAT rise and fall times are measured by min (VIH) and max (VIL), and outputs DAT rise and fall times are measured by min (VOH) and max (VOL). |
Аналогичный номер детали - THGBMHG6C1LBAIL |
|
Аналогичное описание - THGBMHG6C1LBAIL |
|
|
ссылки URL |
| Конфиденциальность |
| ALLDATASHEETRU.COM |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
