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THGBMHG6C1LBAIL датащи(PDF) 25 Page - Toshiba Semiconductor |
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THGBMHG6C1LBAIL датащи(HTML) 25 Page - Toshiba Semiconductor |
25 / 33 page THGBMHG6C1LBAIL 25 Jul. 31th, 2015 Bus Timing Specification in HS400 mode HS400 Input Timing The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode. NOTE VT = 50% of VCCQ, indicates clock reference point for timing measurements. Parameter Symbol Min Max Unit Remark Input CLK Cycle time data transfer mode tPERIOD 5 ns 200 MHz(Max), between rising edges With respect to VT Slew rate SR 1.125 V/ns With respect to VIH /VIL Duty cycle distortion tCKDCD 0.0 0.3 ns Allowable deviation from an ideal 50% duty cycle. With respect to VT Includes jitter, phase noise Minimum pulse width tCKMPW 2.2 ns With respect to VT Input DAT(referenced to CLK) Input set-up time tISUddr 0.4 ns CDEVICE ≤ 6 pF With respect to VIH /VIL Input hold time tIhddr 0.4 ns CDEVICE ≤ 6 pF With respect to VIH /VIL Slew rate SR 1.125 V/ns With respect to VIH /VIL |
Аналогичный номер детали - THGBMHG6C1LBAIL |
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Аналогичное описание - THGBMHG6C1LBAIL |
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