поискавой системы для электроныых деталей |
|
TWR-LS1021A датащи(PDF) 41 Page - Freescale Semiconductor, Inc |
|
TWR-LS1021A датащи(HTML) 41 Page - Freescale Semiconductor, Inc |
41 / 71 page Architecture TWR-LS1021A Reference Manual, Rev. 0 2-26 Freescale Semiconductor 2.20 JTAG port The COP/JTAG architecture is shown in Figure 2-20. Figure 2-20. JTAG/COP connections JTAG commands are accepted from the standard COP/JTAG/CCS header and are sent to LS1021A. JTAG could be accessed by external emulator or MBED. JTAG RST connect to CPLD to generate PORESET signals only at power up. 2.21 GPIO pins The LS1021A has no dedicated GPIO pins; instead, GPIO functions are multiplexed internally on other signals, which must be disabled before using the GPIO functions. Because GPIO is not needed for board operation, GPIO evaluation is strictly limited to validation purposes. In an addition, to remain those GPIO pins primary function, CPLD registers will offer GPIO pin functions for TWR modules control. Table 2-18. GPIO mapping DUT Primary Function DUT GPIO Function Notes GPIO GPIO_3[13] Connect to TWR-ELEV pin A10. GPIO GPIO_3[14] Connect to TWR-ELEV pin B23. ASLEEP, RTC, etc GPIO_1[13:26] Required for non-GPIO function |
Аналогичный номер детали - TWR-LS1021A |
|
Аналогичное описание - TWR-LS1021A |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |