Q0

VCCO

D0

D0

D1

D1

D3

D3

D4

D4 VCCO Q4

Q4

Q0

LOGIC DIAGRAM

25

24

23

22

21

20

19

18

17

16

15

14

13

12

5

6

7

8

9

10

11

26

27

28

2

3

4

Q3

Q3

VCC

Q2

Q2

Q1

Q1

MR

CLK

CLK

VEE

VBB

D2

D2

D0

D0

D1

D1

D2

D2

D3

D3

D4

D4

Q0

Q0

CLK

CLK

MR

VBB

Q1

Q1

Q2

Q2

Q3

Q3

Q4

Q4

D

Q

R

D

Q

R

D

Q

R

D

Q

R

D

Q

R

1

Pinout: 28-Lead PLCC (Top View)

* All VCC and VCCO pins are tied together on the die.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–1

REV 2

12/93

5Bit Differential Register

The MC10E/100E452 is a 5-bit differential register with differential data

(inputs and outputs) and clock. The registers are triggered by a positive

transition of the positive clock (CLK) input. A high on the Master Reset

(MR) asynchronously resets all registers so that the Q outputs go LOW.

The differential input structures are clamped so that the inputs of

unused registers can be left open without upsetting the bias network of

the device. The clamping action will assert the D and the CLK sides of the

inputs. Because of the edge triggered flip-flop nature of the device

simultaneously opening both the clock and data inputs will result in an

output which reaches an unidentified but valid state. Note that the input

clamps only operate when both inputs fall to 2.5V below VCC.

The fully differential design of the device makes it ideal for very high

frequency applications where a registered data path is necessary.

PIN NAMES

Pin

Function

D

[0:4], D[0:4]

Differential Data Inputs

MR

Master Reset Input

CLK, CLK

Differential Clock Input

VBB

VBB Reference Output

Q

[0:4], Q[0:4]

Differential Data Outputs

MC10E452

MC100E452

5-BIT DIFFERENTIAL

REGISTER

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02