поискавой системы для электроныых деталей |
|
DLPC900 датащи(PDF) 20 Page - Texas Instruments |
|
DLPC900 датащи(HTML) 20 Page - Texas Instruments |
20 / 83 page 20 DLPC900 DLPS037D – OCTOBER 2014 – REVISED MARCH 2019 www.ti.com Product Folder Links: DLPC900 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated (1) Refer to I/O Type and Subscript Definition (Table 1). Power and Ground Pin Functions PIN I/O TYPE (1) DESCRIPTION NAME NUMBER VDD33 F20, F17, F11, F8, L21, R21, Y21, PWR 3.3-V I/O power AA19, AA16, AA10, AA7 VDD18 C1, F5, G6, K6, M5, P5, T5, PWR 1.8-V internal DRAMVDD and LVDSAVD I/O power (To shut this power down in a system low-power mode, see the System Power-Up Sequence.) W6, AA5, AE1, H5, N6, T6, AA13, U21, P21, H21, F14 VDDC F19, F16, F13, F10, F7, H6, L6, PWR 1.15-V core power P6, U6, Y6, AA8, AA11, AA14, AA17, AA20, W21, T21, N21, K21, G21, L11, T11, T16, L16 PLLD_VDD L22 PWR 1.15-V DMD clock generator PLL Digital power PLLD_VSS L23 GND 1.15-V DMD clock generator PLL Digital GND PLLD_VAD K25 PWR 1.8-V DMD clock generator PLL Analog power PLLD_VAS K26 GND 1.8-V DMD clock generator PLL Analog GND PLLM1_VDD L26 PWR 1.15-V master-LS clock generator PLL Digital power PLLM1_VSS M22 GND 1.15-V master-LS clock generator PLL Digital GND PLLM1_VAD L24 PWR 1.8-V master-LS clock generator PLL Analog power PLLM1_VAS L25 GND 1.8-V master-LS clock generator PLL Analog GND PLLM2_VDD P23 PWR 1.15-V master-HS clock generator PLL Digital power PLLM2_VSS P24 GND 1.15-V master-HS clock generator PLL Digital GND PLLM2_VAD R25 PWR 1.8-V master-HS clock generator PLL Analog power PLLM2_VAS R26 GND 1.8-V master-HS clock generator PLL Analog GND PLLS_VAD R23 PWR 1.15-V video-2X clock generator PLL Analog power PLLS_VAS R24 GND 1.15-V video-2X clock generator PLL Analog GND L_VDQPAD_[7:0], R_VDQPAD_[7:0] B18, D18, B17, E17, A18, C18, A17, RES DRAM direct test pins (for manufacturing use only). These pins should be tied directly to ground for normal operation. D17, AE17, AC17, AF17, AC18, AB16, AD17, AB17, AD18 CFO_VDD33 AE26 RES DRAM direct test control pin (for manufacturing use only). This pin should be tied directly to 3.3 I/O power (VDD33) for normal operation. VTEST1, VTEST2, VTEST3, VTEST4 AB14, AB15, E15, E16 RES DRAM direct test control pins (for manufacturing use only). These pins should be tied directly to ground for normal operation. LVDS_AVS1, LVDS_AVS2 V5, K5 PWR Dedicated ground for LVDS bandgap reference. These pins should be tied directly to ground for normal operation. VPGM AC6 PWR Fuse programming pin (for manufacturing use only). This pin should be tied directly to ground for normal operation. |
Аналогичный номер детали - DLPC900_V01 |
|
Аналогичное описание - DLPC900_V01 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |