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74AUP1G32 датащи(PDF) 2 Page - NXP Semiconductors

номер детали 74AUP1G32
подробное описание детали  Low-power 2-input OR gate
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74AUP1G32 датащи(HTML) 2 Page - NXP Semiconductors

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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2005
2 of 16
Philips Semiconductors
74AUP1G32
Low-power 2-input OR gate
3.
Quick reference data
[1]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(C
L × VCC
2
× f
o) = sum of the outputs.
[2]
The condition is VI = GND to VCC
4.
Ordering information
5.
Marking
Table 1:
Quick reference data
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3ns.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPHL, tPLH propagation delay
A or B to Y
CL = 5 pF; RL =1MΩ;
VCC = 0.8 V
-
16.8
-
ns
CL = 5 pF; RL =1MΩ;
VCC = 1.1 V to 1.3 V
2.4
5.1
10.9
ns
CL = 5 pF; RL =1MΩ;
VCC = 1.4 V to 1.6 V
1.6
3.6
6.6
ns
CL = 5 pF; RL =1MΩ;
VCC = 1.65 V to 1.95 V
1.4
3.0
5.2
ns
CL = 5 pF; RL =1MΩ;
VCC = 2.3 V to 2.7 V
1.1
2.4
3.9
ns
CL = 5 pF; RL =1MΩ;
VCC = 3.0 V to 3.6 V
1.0
2.1
3.5
ns
Ci
input capacitance
-
0.8
-
pF
CPD
power dissipation
capacitance
VCC = 1.8 V; f = 10 MHz
[1] [2] -
3.5
-
pF
VCC = 3.3 V; f = 10 MHz
[1] [2] -
4.3
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AUP1G32GW
−40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74AUP1G32GM
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads;
6 terminals; body 1
× 1.45 × 0.5 mm
SOT886
Table 3:
Marking
Type number
Marking code
74AUP1G32GW
pG
74AUP1G32GM
pG


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