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TP3054N-X датащи(PDF) 6 Page - National Semiconductor (TI) |
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TP3054N-X датащи(HTML) 6 Page - National Semiconductor (TI) |
6 / 16 page Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40˚C to +85˚C by correlation with 100% electrical testing at T A = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V CC = +5.0V, V BB = –5.0V, TA = 25˚C. All timing parameters are assured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units 1/t PM Frequency of Master Clocks Depends on the Device Used and the 1.536 MHz BCLK R/CLKSEL Pin. 1.544 MHz MCLK X and MCLKR 2.048 MHz t RM Rise Time of Master Clock MCLK X and MCLKR 50 ns t FM Fall Time of Master Clock MCLK X and MCLKR 50 ns t PB Period of Bit Clock 485 488 15725 ns t RB Rise Time of Bit Clock BCLK X and BCLKR 50 ns t FB Fall Time of Bit Clock BCLK X and BCLKR 50 ns t WMH Width of Master Clock High MCLK X and MCLKR 160 ns t WML Width of Master Clock Low MCLK X and MCLKR 160 ns t SBFM Set-Up Time from BCLK X High First Bit Clock after Short Frame 100 ns to MCLK X Falling Edge the Leading Edge of FS X Long Frame 125 t SFFM Setup Time from FS X High to MCLK X Falling Edge Long Frame Only 100 ns t WBH Width of Bit Clock High V IH=2.2V 160 ns t WBL Width of Bit Clock Low V IL=0.6V 160 ns t HBFL Holding Time from Bit Clock Long Frame Only 0 ns Low to Frame Sync t HBFS Holding Time from Bit Clock Short Frame Only 0 ns High to Frame Sync t SFB Set-Up Time from Frame Sync Long Frame Only 115 ns to Bit Clock Low t DBD Delay Time from BCLK X High Load=150 pF plus 2 LSTTL Loads 0 140 ns to Data Valid t DBTS Delay Time to TS X Low Load=150 pF plus 2 LSTTL Loads 140 ns t DZC Delay Time from BCLK X Low to C L=0 pF to 150 pF 50 165 ns Data Output Disabled t DZF Delay Time to Valid Data from C L=0 pF to 150 pF 20 165 ns FS X or BCLKX, Whichever Comes Later t SDB Set-Up Time from D R Valid to 50 ns BCLK R/X Low t HBD Hold Time from BCLK R/X Low to 50 ns D R Invalid t SF Set-Up Time from FS X/R to Short Frame Sync Pulse (1 Bit Clock 50 ns BCLK X/R Low Period Long) t HF Hold Time from BCLK X/R Low Short Frame Sync Pulse (1 Bit Clock 100 ns to FS X/R Low Period Long) t HBFl Hold Time from 3rd Period of Long Frame Sync Pulse (from 3 to 8 Bit 100 ns Bit Clock Low to Frame Sync Clock Periods Long) (FS X or FSR) t WFL Minimum Width of the Frame 64k Bit/s Operating Mode 160 ns Sync Pulse (Low Level) www.national.com 6 |
Аналогичный номер детали - TP3054N-X |
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Аналогичное описание - TP3054N-X |
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