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MC14569BDT датащи(PDF) 1 Page - ON Semiconductor

номер детали MC14569BDT
подробное описание детали  Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter
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производитель  ONSEMI [ON Semiconductor]
домашняя страница  http://www.onsemi.com
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© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14569B/D
MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable divide–by–N dual 4–bit binary
or BCD down counter constructed with MOS P–channel and
N–channel enhancement mode devices (complementary MOS) in a
monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase–locked loops,
and other frequency division applications requiring low power
dissipation and/or high noise immunity.
Speed–up Circuitry for Zero Detection
Each 4–Bit Counter Can Divide Independently in BCD or Binary
Mode
Can be Cascaded With MC14526B for
Frequency Synthesizer Applications
All Outputs are Buffered
Schmitt Triggered Clock Conditioning
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 2.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14569BCP
PDIP–16
2000/Box
MC14569BDT
TSSOP–16
96/Rail
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14569BCP
AWLYYWW
SOIC–16
DW SUFFIX
CASE 751G
1
16
14569B
AWLYYWW
MC14569BDW
SOIC–16
47/Rail
MC14569BDWR2
SOIC–16
1000/Tape & Reel
TSSOP–16
DT SUFFIX
CASE 948F
14
569B
ALYW
1
16


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