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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADC081500EVAL датащи(PDF) 10 Page - National Semiconductor (TI) |
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ADC081500EVAL датащи(HTML) 10 Page - National Semiconductor (TI) |
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10 / 28 page  Converter Electrical Characteristics (Continued) The following specifications apply after calibration for V A =VDR = +1.9VDC, OutV = 1.9V, VIN (a.c. coupled) Full Scale Range = differential 870mV P-P,CL = 10 pF, Differential (a.c. coupled) sinewave input clock, fCLK = 1.5 GHz at 0.5VP-P with 50% duty cycle, V BG = Floating, Normal Control Mode, Single Data Rate Mode, REXT = 3300 Ω ±0.1%, Analog Signal Source Impedance = 100 Ω Differential. Boldface limits apply for T A =TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) AC ELECTRICAL CHARACTERISTICS Input Clock Duty Cycle 200 MHz ≤ Input clock frequency ≤ 1.5 GHz (Note 12) 50 20 80 % (min) % (max) t CL Input Clock Low Time (Note 11) 333 133 ps (min) t CH Input Clock High Time (Note 11) 333 133 ps (min) DCLK Duty Cycle (Note 11) 50 45 55 % (min) % (max) t RS Reset Setup Time (Note 11) 150 ps t RH Reset Hold Time (Note 11) 250 ps t SD Syncronizing Edge to DCLK Output Delay f CLKIN = 1.5 GHz f CLKIN = 200 MHz 3.53 3.85 ns t RPW Reset Pulse Width (Note 11) 4 Clock Cycles (min) t LHT Differential Low to High Transition Time 10% to 90%, C L = 2.5 pF 250 ps t HLT Differential High to Low Transition Time 10% to 90%, C L = 2.5 pF 250 ps t OSK DCLK to Data Output Skew 50% of DCLK transition to 50% of Data transition, SDR Mode and DDR Mode, 0˚ DCLK (Note 11) ±50 ps (max) t SU Data to DCLK Set-Up Time DDR Mode, 90˚ DCLK (Note 11) 1 ns t H DCLK to Data Hold Time DDR Mode, 90˚ DCLK (Note 11) 1 ns t AD Sampling (Aperture) Delay Input CLK+ Fall to Acquisition of Data 1.3 ns t AJ Aperture Jitter 0.4 ps rms t OD Input Clock to Data Output Delay (in addition to Pipeline Delay) 50% of Input Clock transition to 50% of Data transition 3.1 ns Pipeline Delay (Latency) (Notes 11, 14) D Outputs 13 Input Clock Cycles Dd Outputs 14 Over Range Recovery Time Differential V IN step from ±1.2V to 0V to get accurate conversion 1 Input Clock Cycle t WU PD low to Rated Accuracy Conversion (Wake-Up Time) 500 ns f SCLK Serial Clock Frequency (Note 11) 100 MHz t SSU Data to Serial Clock Setup Time (Note 11) 2.5 ns (min) t SH Data to Serial Clock Hold Time (Note 11) 1 ns (min) Serial Clock Low Time 4 ns (min) Serial Clock High Time 4 ns (min) t CAL Calibration Cycle Time 1.4 x 10 5 Clock Cycles t CAL_L CAL Pin Low Time See Figure 9 (Note 11) 80 Clock Cycles (min) t CAL_H CAL Pin High Time See Figure 9 (Note 11) 80 Clock Cycles (min) www.national.com 10 |
Аналогичный номер детали - ADC081500EVAL |
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Аналогичное описание - ADC081500EVAL |
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