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TSC8051C1XXX-A-12IDR датащи(PDF) 4 Page - TEMIC Semiconductors |
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TSC8051C1XXX-A-12IDR датащи(HTML) 4 Page - TEMIC Semiconductors |
4 / 31 page TSC8051C1 Rev. D (14 Jan. 97) 4 MATRA MHS 5. Pin Description VSS Circuit ground. VCC Power supply voltage. RST A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits power–on reset using only a capacitor connected to VCC. PORT 0 (P0.0–P0.7) Port 0 is an 8–bit open–drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high–impedance inputs. Port 0 is also the multiplexed low–order address and data bus during access to external Program and Data memory. In this application it uses strong internal pull–up when emitting 1’s. Port 0 can sink and source 8 LS TTL loads. PORT 1 (P1.0–P1.7) Port 1 is an 8–bit bidirectional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL on the data–sheet) because of the internal pullups. Port 1 also serves 4 programmable PWM open drain outputs, as listed below: Port Pin Alternate Function P1.0 PWM8: Pulse Width Modulation output 8. P1.1 PWM9: Pulse Width Modulation output 9. P1.2 PWM10: Pulse Width Modulation output 10. P1.3 PWM11: Pulse Width Modulation output 11. Port 1 can sink and source 3 LS TTL loads. PORT 2 (P2.0–P2.7) Port 2 is an 8–bit bidirectional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL on the data–sheet) because of the internal pullups. Port 2 emits the high–order 8–bit address during fetches from external Program Memory and during accesses to external Data Memory that use 16–bit addresses. In this application it uses strong internal pull–up when emitting 1’s. Port 2 can sink and source 3 LS TTL loads. PORT 3 (P3.0–P3.7) Port 3 is an 8–bit bidirectional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL on the data–sheet) because of the internal pullups. Each line on this port has 2 or 3 functions either a general I/O or special control signal, as listed below: Port Pin Alternate Function P3.0 RXD: serial input port. P3.1 TXD: serial output port. P3.2 INT0: external interrupt 0. VSYNC: vertical synchro input. P3.3 INT1: external interrupt 1. VOUT: buffered V-SYNC output. P3.4 T0: Timer 0 external input. HSYNC: horizontal synchro input. P3.5 T1: Timer 1 external input. HOUT: buffered H–SYNC output. P3.6 WR: external data memory write strobe. SCL: serial port clock line I2C bus. P3.7 RD: external data memory read strobe. SDA: serial port data line I2C bus. Port 3 can sink and source 3 LS TTL loads. PWM0–7 These eight Pulse Width Modulation outputs are true open drain outputs and are floating after reset. ALE The Address Latch Enable output signal occurs twice each machine cycle except during external data memory access. The negative edge of ALE strobes the address into external data memory or program memory. ALE can sink and source 8 LS TTL loads. If desired, ALE operation can be disabled by setting bit 0 of SFR location AFh (MSCON). With the bit set, ALE is active only during MOVX instruction and external fetches. Otherwise the pin is pulled low. |
Аналогичный номер детали - TSC8051C1XXX-A-12IDR |
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Аналогичное описание - TSC8051C1XXX-A-12IDR |
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