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TSC51C1XXX-A-16IDR датащи(PDF) 6 Page - TEMIC Semiconductors

номер детали TSC51C1XXX-A-16IDR
подробное описание детали  8-Bit Microcontroller for Digital Computer Monitors
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производитель  TEMIC [TEMIC Semiconductors]
домашняя страница  http://www.temic.de
Logo TEMIC - TEMIC Semiconductors

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TSC8051C1
Rev. D (14 Jan. 97)
6
MATRA MHS
6. Basic Functional Description
6.1. Idle And Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the
interrupt, serial port, and timer blocks to continue to
operate while the clock to the CPU is gated off.
These special modes are activated by software via the
Special Function Register, its hardware address is 87h.
PCON is not bit addressable.
OSC
CLOCK
GEN.
INTERRUPT
SERIAL PORT
TIMER
BLOCKS
CPU
IDL
XTAL2
XTAL1
PD
Figure 3. Idle and Power Down Hardware.
PCON: Power Control Register
MSB
SFR 87h
LSB
SMOD
GF1
GF0
PD
IDL
Symbol
Position
Name and Function
IDL
PCON.0
Idle mode bit. Setting this bit activates idle mode operation.
PD
PCON.1
Power Down bit. Setting this bit activates power down operation.
GF0
PCON.2
General–purpose flag bit.
GF1
PCON.3
General–purpose flag bit.
PCON.4
(Reserved).
PCON.5
(Reserved).
PCON.6
(Reserved).
SMOD
PCON.7
Double Baud rate bit. Setting this bit causes the baud rate to double when the serial port
is being used in either modes 1, 2 or 3.
If 1’s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is 0XXX0000b.
6.1.1. Idle Mode
The instruction that sets PCON.0 is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety: the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM, and all other register maintain their
data during Idle Table 1 describes the status of the
external pins during Idle mode.
There are two ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON.0
to be cleared by hardware terminating Idle mode. The
interrupt is serviced, and following RETI, the next
instruction to be executed will be the one following the
instruction that wrote 1 to PCON.0.
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear
one or both flag bits. When Idle mode is terminated by
an enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.


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