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SN74LV4320AGKFR датащи(PDF) 1 Page - Texas Instruments |
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SN74LV4320AGKFR датащи(HTML) 1 Page - Texas Instruments |
1 / 23 page SN74LV4320A LOW POWER, DUALSUPPLY, LEVELTRANSLATING CompactFlash INTERFACE WITH 16BIT DATA, 11BIT ADDRESS, AND 13BIT CONTROL LINES SCES628A − APRIL 2005 − REVISED APRIL 2005 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Member of the Texas Instruments Widebus+ Family D Designed to Optimize Power Savings in Portable Applications D 1.65-V to 5.5-V Level Translation Using Dual Supplies D Matched Pinout With CompactFlash (CF) Connector Pin Configurations to Optimize PCB Layout D Input-Disable Feature Allows Floating Input Conditions D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD − 15-kV Human-Body Model − +4-kV IEC61000-4-2, Contact Discharge (Latch-Up Immune) description/ordering information This CompactFlash (CF) interface chip is designed to provide a single-chip solution for CF card interfaces. Separate VCC rails for the system bus side and the CF connector bus side allow voltage-level shifting. This is helpful for interfacing between a core chipset, which may operate from 3.3 V down to 1.65 V, and CF cards, which operate from 3.3-V or 5-V supply voltages. All the input buffers feature the input-disable function, which allows conditional floating input signals. The input, output, and I/O buffers on the CF connector side have been defined to comply with CF+ and CompactFlash specification revisions 1.4 and 2.0. This device has 16-bit data lines and 24-bit address/command lines. CD1 and CD2 have internal pullup resistors to pull them to a high logic state if there is no card in the CF slot. The presence of a CF card in the CF card slot generates a low logic signal at SCD. A separate power-supply pin, VCC_SD, controls the SCD output buffer. The SCD signal can be used to control a voltage regulator, which may power the CF slot and the CF side of this device. VCC_SD is particularly helpful when the core processor operates at a low VCC, but the regulator needs a higher control signal voltage. The MASTER_EN signal controls all the buffers and transceivers except CD1 and CD2. If MASTER_EN is high, the SN74LV4320A is in a power-down mode. The BUF_EN signal, in conjunction with MASTER_EN, controls the 11-bit address lines and 13-bit control/command lines. The 16-bit data lines use two separate enable signals. ENL, in conjunction with MASTER_EN, controls the lower 8-bit data lines (D07−D00). ENH, in conjunction with MASTER_EN, controls the upper 8-bit data lines (D15−D08). A DIR(S/CF) input controls the data direction between the system bus and the CF card. An additional DIR_OUT pin generates the DIR(S/CF) signal using the SOE and SIORD signals. With either SOE or SIORD being low, the data direction is from the CF card side to the system side (DIR_OUT = L). DIR(S/CF) and DIR_OUT are placed adjacent to each other, which is convenient for connecting DIR(S/CF) and DIR_OUT, if DIR_OUT is used. This saves an additional signal from the system controller to control the data direction. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING −40 °C to 85°C LFBGA − GKF Tape and reel SN74LV4320AGKFR LM320A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. CompactFlash is a trademark of Sandisk Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Аналогичный номер детали - SN74LV4320AGKFR |
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Аналогичное описание - SN74LV4320AGKFR |
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