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MSP430F5507 датащи(PDF) 35 Page - Texas Instruments |
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MSP430F5507 датащи(HTML) 35 Page - Texas Instruments |
35 / 125 page 35 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Specifications Copyright © 2009–2020, Texas Instruments Incorporated 5.25 PMM, SVM Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(SVML) SVML current consumption SVMLE = 0, PMMCOREV = 2 0 nA SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200 SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 1.5 µA tpd(SVML) SVML propagation delay SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5 µs SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20 t(SVML) SVML on or off delay time SVMLE = 0 → 1, SVMLFP = 1 12.5 µs SVMLE = 0 → 1, SVMLFP = 0 100 (1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide. (2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx Family User's Guide. (3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the performance mode settings as for LPM2, LPM3, and LPM4. (4) This value represents the time from the wake-up event to the reset vector execution. 5.26 Wake-up Times From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tWAKE-UP-FAST Wake-up time from LPM2, LPM3, or LPM4 to active mode(1) PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 1 fMCLK ≥ 4.0 MHz 5 µs fMCLK < 4.0 MHz 6 tWAKE-UP-SLOW Wake-up time from LPM2, LPM3, or LPM4 to active mode(2)(3) PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3), SVSLFP = 0 150 165 µs tWAKE-UP-LPM5 Wake-up time from LPM4.5 to active mode(4) 2 3 ms tWAKE-UP-RESET Wake-up time from RST or BOR event to active mode(4) 2 3 ms 5.27 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT fTA Timer_A input clock frequency Internal: SMCLK or ACLK, External: TACLK, Duty cycle = 50% ±10% 1.8 V, 3 V 25 MHz tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture. 1.8 V, 3 V 20 ns 5.28 Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT fTB Timer_B input clock frequency Internal: SMCLK or ACLK, External: TBCLK, Duty cycle = 50% ±10% 1.8 V, 3 V 25 MHz tTB,cap Timer_B capture timing All capture inputs, Minimum pulse duration required for capture 1.8 V, 3 V 20 ns |
Аналогичный номер детали - MSP430F5507 |
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Аналогичное описание - MSP430F5507 |
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