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EP2AGX45DF25I5 датащи(PDF) 62 Page - Altera Corporation |
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EP2AGX45DF25I5 датащи(HTML) 62 Page - Altera Corporation |
62 / 90 page 1–54 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation fOUT Output frequency for internal global or regional clock (–4 Speed Grade) — — 500 MHz Output frequency for internal global or regional clock (–5 Speed Grade) — — 500 MHz Output frequency for internal global or regional clock (–6 Speed Grade) — — 400 MHz fOUT_EXT Output frequency for external clock output (–4 Speed Grade) — — 670 (5) MHz Output frequency for external clock output (–5 Speed Grade) — — 622 (5) MHz Output frequency for external clock output (–6 Speed Grade) — — 500 (5) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tOUTPJ_DC Dedicated clock output period jitter (fOUT 100 MHz) — — 300 ps (p–p) Dedicated clock output period jitter (fOUT 100 MHz) — — 30 mUI (p–p) tOUTCCJ_DC Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz) — — 300 ps (p–p) Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz) — — 30 mUI (p–p) fOUTPJ_IO Regular I/O clock output period jitter (fOUT 100 MHz) — — 650 ps (p–p) Regular I/O clock output period jitter (fOUT 100 MHz) — — 65 mUI (p–p) fOUTCCJ_IO Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz) — — 650 ps (p–p) Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz) — — 65 mUI (p–p) tCONFIGPLL Time required to reconfigure PLL scan chains — 3.5 — SCANCLK cycles tCONFIGPHASE Time required to reconfigure phase shift — 1 — SCANCLK cycles fSCANCLK SCANCLK frequency — — 100 MHz tLOCK Time required to lock from end of device configuration — — 1 ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) —— 1 ms fCL B W PLL closed-loop low bandwidth — 0.3 — MHz PLL closed-loop medium bandwidth — 1.5 — MHz PLL closed-loop high bandwidth — 4 — MHz tPLL_PSERR Accuracy of PLL phase shift — — ±50 ps tARESET Minimum pulse width on areset signal 10 — — ns Table 1–44. PLL Specifications for Arria II GX Devices (Part 2 of 3) Symbol Description Min Typ Max Unit |
Аналогичный номер детали - EP2AGX45DF25I5 |
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Аналогичное описание - EP2AGX45DF25I5 |
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