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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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JN5189 датащи(PDF) 36 Page - NXP Semiconductors |
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JN5189 датащи(HTML) 36 Page - NXP Semiconductors |
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36 / 92 page  JN5189 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1.2 — June 2020 36 of 92 NXP Semiconductors IEEE 802.15.4 low power wireless MCU JN5189(T)/JN5188(T) • 28-bit and 41-bit down counter • Optionally runs during power-down periods • Clocked by 32 kHz system clock; either 32 kHz RC oscillator, or 32 kHz XTAL oscillator • Time-out period in excess of 1 year is possible A wake-up timer consists of a 28-bit or 41-bit down counter clocked from the selected 32 kHz clock. An interrupt or wake-up event can be generated when the counter reaches zero. On reaching zero, the counter will continue to count down until stopped, which allows the latency in responding to the interrupt to be measured. If an interrupt or wake-up event is required, the timer interrupt should be enabled before loading the count value for the period. Once the counter value has been loaded and the counter started, the count-down begins. The counter can be stopped at any time through software control - the counter will remain at the value that it contained when it was stopped and no interrupt will be generated. The status of the timers can be read to indicate if the timers are running and/or have expired; this is useful when the timer interrupts are masked. 8.11 USART There are 2 USART interfaces to provide Synchronous and Asynchronous serial communications with external devices. A range of features and flexible baud rate control supports a range of applications. • 2 USART interfaces, 1 with flow control • 7, 8 or 9 data bits and 1 or 2 stop bits • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option • Multiprocessor/multidrop (9-bit) mode with software address compare • RS-485 transceiver output enable • Parity generation and checking: odd, even, or none • Software selectable oversampling from 5 to 16 clocks in asynchronous mode • One transmit and one receive data buffer • The USART function supports separate transmit and receive FIFO with 4 entries each • RTS/CTS supported on one USART. This allows for hardware signaling for automatic flow control. Software flow control can be performed using delta CTS detect, transmit disable control, and any GPIO as an RTS output • Break generation and detection • Receive data is 2 of 3 sample "voting". status flag set when one sample differs • Built-in baud rate generator with auto-baud function • A fractional rate divider is shared among all USARTs • Interrupts available for FIFO receive level reached, FIFO transmit level reached, receiver idle, change in receiver break detect, framing error, parity error, overrun, underrun, delta CTS detect, and receiver sample noise detected • Loopback mode for testing of data and flow control • USART transmit and receive functions can operate with the system DMA controller |
Аналогичный номер детали - JN5189 |
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Аналогичное описание - JN5189 |
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