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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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JN5189 датащи(PDF) 67 Page - NXP Semiconductors |
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JN5189 датащи(HTML) 67 Page - NXP Semiconductors |
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67 / 92 page  JN5189 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1.2 — June 2020 67 of 92 NXP Semiconductors IEEE 802.15.4 low power wireless MCU JN5189(T)/JN5188(T) 14.11 I2C timing [1] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [2] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [3] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [4] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [5] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [6] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [7] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. [8] Valid for I2C IO cells. When I2C functionality is supported on standard IO cells this Min time is 0. Table 39. I2C timing VDDE = 1.9 V to 3.6 V; Tj = −40°C to +125°C; unless otherwise specified; guaranteed by design. Not tested in production. Symbol Parameter Conditions Min Typ Max Unit fSCL SC clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode plus 0 1 MHz tf Fall time, of both SDA and SCL signals Standard-mode 300 ns Fast-mode [8] 20 x VDDE/5.5 300 ns Fast-mode plus 120 ns tLOW Low period of the SCL clock Standard-mode 4.7 s Fast-mode 1.3 s Fast-mode plus 0.5 s tHIGH High period of the SCL clock Standard-mode 4 s Fast-mode 0.6 s Fast-mode plus 0.26 s tHD;DAT Data hold time Standard-mode 0 ns Fast-mode 0 ns Fast-mode plus 0 ns tSU;DAT Data setup time Standard-mode 250 ns Fast-mode 100 ns Fast-mode plus 50 ns |
Аналогичный номер детали - JN5189 |
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Аналогичное описание - JN5189 |
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