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CC3230S датащи(PDF) 28 Page - Texas Instruments |
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CC3230S датащи(HTML) 28 Page - Texas Instruments |
28 / 104 page Table 7-2. Pin Multiplexing (continued) Register Address Register Name Pin ANALOG OR SPECIAL FUNCTION Digital Function (XXX Field Encoding)(1) JTAG Hostless Mode BLE COEX 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CC_COEX _SW_OUT CC_COEX _BLE_IN 0x4402 E10C GPIO_PAD_ CONFIG_27 30 — — — — ANTSEL 2(3) — — — — — — — — — — — — — 0x4402 E11C GPIO_PAD_ CONFIG_31 45(4) (3) — Y Y Y GPIO31 — UART1_ RX — — — McAXR0 GSPI_CL K — UART0_ RX — — McAFSX — 0x4402 E0A0 GPIO_PAD_ CONFIG_0 50 — Y Y Y GPIO0 — — UART0_ RTS McAXR0 — McAXR1 GT_ CCP00 — GSPI_ CS UART1_ RTS — UART0_ CTS — 0x4402 E120 GPIO_PAD_ CONFIG_32 52 — Y(4) Y(4) Y(4) GPIO32 — McACLK — McAXR0 — UART0_ RTS — GSPI_ MOSI — — — — — 0x4402 E118 GPIO_PAD_ CONFIG_30 53 -— Y(4) Y(4) Y(4) GPIO30 — McACLK McAFSX GT_ CCP05 — — GSPI_ MISO — UART0_ TX — — — — 0x4402 E0A4 GPIO_PAD_ CONFIG_1 55 — — — — GPIO1 — — UART0_ TX pCLK (PIXCLK) — UART1_ TX GT_ CCP01 — — — — — — 0x4402 E0A8 GPIO_PAD_ CONFIG_2 57 — — — — GPIO2 — — UART0_ RX — — UART1_ RX GT_ CCP02 — — — — — — 0x4402 E0AC GPIO_PAD_ CONFIG_3 58 — Y(5) Y — GPIO3 — — — pDATA7 (CAM_D3) — UART1_ TX — — — — — — — 0x4402 E0B0 GPIO_PAD_ CONFIG_4 59 — Y(5) Y — GPIO4 — — — pDATA6 (CAM_D2) — UART1_ RX — — — — — — — 0x4402 E0B4 GPIO_PAD_ CONFIG_5 60 — Y Y Y GPIO5 — — — pDATA5 (CAM_D1) — McAXR1 GT_ CCP05 — — — — — — 0x4402 E0B8 GPIO_PAD_ CONFIG_6 61 — Y Y Y GPIO6 — — UART1_ CTS pDATA4 (CAM_D0) UART0_ RTS UART0_ CTS GT_ CCP06 — — — — — — 0x4402 E0BC GPIO_PAD_ CONFIG_7 62 — — — — GPIO7 — — UART1_ RTS — — — — — — UART0_ RTS UART0_ TX — McACLKX 0x4402 E0C0 GPIO_PAD_ CONFIG_8 63 — Y Y Y GPIO8 — — — — — SDCARD_ IRQ McAFSX — — — — GT_ CCP06 — 0x4402 E0C4 GPIO_PAD_ CONFIG_9 64 -— Y Y Y GPIO9 — — GT_ PWM05 — — SDCARD_ DATA0 McAXR0 — — — — GT_ CCP00 — (1) Pin mux encodings with (RD) denote the default encoding after reset release. (2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only. (3) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For the CC3230S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47. (4) LPDS retention unavailable. (5) Output Only CC3230S, CC3230SF SWRS226 – FEBRUARY 2020 www.ti.com 28 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CC3230S CC3230SF |
Аналогичный номер детали - CC3230S |
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Аналогичное описание - CC3230S |
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