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RM48L940 датащи(PDF) 54 Page - Texas Instruments |
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RM48L940 датащи(HTML) 54 Page - Texas Instruments |
54 / 174 page 3.3 V V CCIOPORH 1.2 V V CCPORH V CCIOPORL V (1.2 V) V / V (3.3 V) CC CCIO CCP nPORRST 8 6 6 7 7 9 3 V CCPORL V IL(PORRST) V / V CCIO CCP V CC V CCPORL V IL(PORRST) V IL V IL V IL V CCIOPORH V CCPORH V CCIOPORL NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing. RM48L940, RM48L740, RM48L540 SPNS175C – APRIL 2012 – REVISED JUNE 2015 www.ti.com 6.3.2 Power-Down Sequence The different supplies to the device can be powered down in any order. 6.3.3 Power-On Reset: nPORRST This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown. 6.3.3.1 nPORRST Electrical and Timing Requirements Table 6-4. Electrical Requirements for nPORRST NO. PARAMETER MIN MAX UNIT VCCPORL VCC low supply level when nPORRST must be active during power up 0.5 V VCC high supply level when nPORRST must remain active during power VCCPORH 1.14 V up and become active during power down VCCIO / VCCP low supply level when nPORRST must be active during VCCIOPORL 1.1 V power up VCCIO / VCCP high supply level when nPORRST must remain active VCCIOPORH 3.0 V during power up and become active during power down VIL(PORRST) Low-level input voltage of nPORRST VCCIO > 2.5V 0.2 * VCCIO V Low-level input voltage of nPORRST VCCIO < 2.5V 0.5 V Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during 3 tsu(PORRST) 0 ms power up 6 th(PORRST) Hold time, nPORRST active after VCC > VCCPORH 1 ms 7 tsu(PORRST) Setup time, nPORRST active before VCC < VCCPORH during power down 2 µs 8 th(PORRST) Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH 1 ms 9 th(PORRST) Hold time, nPORRST active after VCC < VCCPORL 0 ms Filter time nPORRST pin; tf(nPORRST) 500 2000 ns pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset. Figure 6-1. nPORRST Timing Diagram 54 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
Аналогичный номер детали - RM48L940_V01 |
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Аналогичное описание - RM48L940_V01 |
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