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74ABT3284VJG датащи(PDF) 3 Page - National Semiconductor (TI) |
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74ABT3284VJG датащи(HTML) 3 Page - National Semiconductor (TI) |
3 / 12 page Function Tables Output Enable Control Table Inputs Outputs Control Mode Function OE (A B C D X Y) MODE SO CP IN Port A B C D X Y L L X ENABLE ASYNC ENABLED OUTPUT IO input always active H L X DISABLE ASYNC DISABLED OUTPUT IO input always active (Notes 2 3) H (Note 1) L (Note 3) SYNC (Note 3) Note 1 Low to High transitions of MODE SO must be immediately preceeded by a low to high transition (clock edge) on CP IN while holding Synchronous Control Inputs OE (A B C D X Y) steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous Note 2 OE (A B C D X Y) levels are synchronously asserted by the positive transition of CP IN when MODE SO is high Note 3 Synchronous Control Mode Functions are same as Asynchronous at time T a 1ofCP IN A Side Data Path Select Function Table Inputs Data Path Control Mode Function ASEL(1) ASEL(0) MODE SC CP IN From To RegPort Port L L L X (A B C D) IR A B C D ASYNC Readback Contents of Input Register (A B C D) IR to Port (A B C D) L H L X (A B C D) OR A B C D ASYNC Clocked Path Contents of Output Register (A B C D) OR to Port (A B C D) H L L X Port X A B C D ASYNC Transparent Path Port X to Port A B C D H H L X Port X A C ASYNC Transparent Path Port X to Port A C Port Y B D Transparent Path Port Y to Port B D (Notes 2 3) (Notes 2 3) H (Note 1) L (Note 3) (Note 3) SYNC (Note 3) Note 1 Low to High transitions of MODE SC must be immediately preceeded by a low to high transition (clock edge) on CP IN while holding Synchronous Control Inputs ASEL(0) and ASEL(1) steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous Note 2 ASEL(0) and ASEL(1) levels are synchronously asserted by the positive transition of CP IN when MODE SC is high Note 3 Synchronous Control Mode Functions are same as Asynchronous at time T a 1ofCP IN Input Register Control Table Inputs Register Control Mode Function Port LD(A B C D) I MODE SC CP IN CP XA (A B C D) IR (A B C D) XL L X L HOLD ASYNC HOLD Input Register holds previous state L (H) H L X L L (H) ASYNC LOAD Port A B C D clocked to Input Register (A B C D) IR via CP AX positive edge (Note 3) (Notes 2 3) H (Note 1) L (Note 3) (Note 3) SYNC (Note 3) Note 1 Low to High transitions of MODE SO must be immediately preceeded by a low to high transition (clock edge) on CP IN while holding Synchronous Control Inputs LDAI LDBI LDCI and LDDI steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous Note 2 LDAI LDBI LDCI and LDDI levels are synchronously asserted by the positive transition of CP IN when MODE SC is high Note 3 Synchronous Control Mode Functions are same as Asynchronous at time T a 1ofCP IN 3 |
Аналогичный номер детали - 74ABT3284VJG |
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Аналогичное описание - 74ABT3284VJG |
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