TSZ02201-0P2P0B001840-1-2

16.Nov.2020 Rev.005

TSZ22111 • 15 • 001

20/36

BD64008MUV

© 2017 ROHM Co., Ltd. All rights reserved.

www.rohm.com

Pre Driver

Soft Start DAC

OSC

VBBSW1

gmAMP

R1

R2

L

C1

R

S

Q

Current

Detection

SWOUT1

Explanation of Block Operation – continued

3

SWREG

Figure 9. SWREG1 Block Diagram (SWREG2: Synchronous and VBBSW → VINSW2)

3.1

Basic Operation

This IC incorporates 2ch of switching regulator circuit that repeats ON/OFF, synchronized with an internal clock

(SWCLK), 1ch SWREG operates by 250 kHz (Typ) ±15 % and 2ch SWREG operates by 1 MHz (Typ) ±20 %.

and ENBSW2 = H, the IC doesn’t work.

Output voltage is determined with external resistance by using the following equation:

is the output voltage.

is the FB1 voltage.

is the external resistance.

accomplished using the equation below:

⁄

⁄

:

is the output ripple voltage.

:

is the output ripple current.

ESR

:

is the equivalent series resistance.

:

is the switching frequency.

:

is the output capacitance.

⁄

⁄

[A]

L

:

is the inductance.

:

is the applied voltage.

3.2

Skip Mode Operation

In certain run modes, such as when output load is low, gmAMP output (COMP) voltage exceeds the current

detection level at the SWCLK rising edge. In this case, output will not switch ON.

3.3

MAX DUTY

In certain run modes, such as when output load is high, if the COMP voltage level does not reach the current

detection level, output MAX DUTY (90 %) will force the output OFF.