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74AVCH4T245PWRE4 датащи(PDF) 2 Page - Texas Instruments |
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74AVCH4T245PWRE4 датащи(HTML) 2 Page - Texas Instruments |
2 / 17 page SN74AVCH4T245 4BIT DUALSUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3STATE OUTPUTS SCES577A – JUNE 2004 – REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING QFN − RGY Tape and reel SN74AVCH4T245RGYR WS245 SOIC − D Tube SN74AVCH4T245D AVCH4T245 −40 °C to 85°C SOIC − D Tape and reel SN74AVCH4T245DR AVCH4T245 −40 °C to 85°C TSSOP − PW Tube SN74AVCH4T245PW WS245 TSSOP − PW Tape and reel SN74AVCH4T245PWR WS245 TVSOP − DGV Tape and reel SN74AVCH4T245DGVR WS245 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each 4-bit section) INPUTS OPERATION OE DIR OPERATION L L B data to A bus L H A data to B bus H X All output Hi-Z logic diagram (positive logic) 1DIR 1OE 1A1 1B1 2 4 15 13 1A2 1B2 5 12 2DIR 2OE 2A1 2B1 3 6 14 11 2A2 2B2 7 10 |
Аналогичный номер детали - 74AVCH4T245PWRE4 |
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Аналогичное описание - 74AVCH4T245PWRE4 |
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