поискавой системы для электроныых деталей |
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SII164 датащи(PDF) 4 Page - Silicon image |
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SII164 датащи(HTML) 4 Page - Silicon image |
4 / 33 page SiI 164 PanelLink Transmitter Data Sheet SiI-DS-0021-C iv LIST OF TABLES Table 1. Sample Programming Sequence for SiI 164................................................................................... 17 Table 2. Non I 2C Strapping Mode Options.................................................................................................... 19 Table 3. One Pixel/Clock Input/Output TFT Mode - VESA P&D and FPDI-2 TM Compliant........................... 20 Table 4. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode ................................ 21 Table 5. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode ................................ 22 Table 6. Recommended Components for Bypass and Decoupling Circuits ................................................. 25 LIST OF FIGURES Figure 1. Pin Diagram for SiI 164 ................................................................................................................... 1 Figure 2. Functional Block Diagram................................................................................................................ 2 Figure 3. Clock Cycle High/Low Times ........................................................................................................... 6 Figure 4. Low Swing Differential Times .......................................................................................................... 6 Figure 5. ISEL/RST# Minimum Timing ........................................................................................................... 6 Figure 6. Input Data Setup/Hold Time to IDCK............................................................................................... 7 Figure 7. VSYNC, HSYNC and CTL[3:1] Delay Time from DE....................................................................... 7 Figure 8. DE High and Low Times .................................................................................................................. 7 Figure 9. I 2C Data Valid Delay (driving Read Cycle data)............................................................................... 7 Figure 10. I 2C Byte Read .............................................................................................................................. 14 Figure 11. I 2C Byte Write .............................................................................................................................. 14 Figure 12. SiI 164 Data De-skew Feature Timing......................................................................................... 15 Figure 13. 12 bit Input Data Latching............................................................................................................ 16 Figure 14. 24 bit Input Data Latching............................................................................................................ 16 Figure 15. Non I 2C Mode Schematic Example ............................................................................................. 18 Figure 16. I 2C Bus Voltage Level-Shifting using Fairchild NDC7002N ......................................................... 23 Figure 17. I 2C Bus Voltage Level Shifting using Philips GTL 2010............................................................... 23 Figure 18. Voltage Regulation using TL431.................................................................................................. 24 Figure 19. Voltage Regulation using LM317 ................................................................................................. 24 Figure 20. Decoupling and Bypass Capacitor Placement ............................................................................25 Figure 21. Decoupling and Bypass Schematic ............................................................................................. 25 Figure 22. Series Input Damping Resistors for Driving Source ....................................................................26 Figure 23. Example of Incorrect Differential Signal Routing ......................................................................... 26 Figure 24. Example of Correct Differential Signal Routing ........................................................................... 27 Figure 25. Differential Trace Routing to DVI Connector(Top Side View) ...................................................... 27 Figure 26. 64-pin TQFP Package Dimensions (JEDEC code MS-026ED) .................................................. 28 |
Аналогичный номер детали - SII164 |
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Аналогичное описание - SII164 |
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