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TDA9952HN датащит (Datasheet) 9 Page - NXP Semiconductors

№ деталь TDA9952HN
подробность  10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
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 9 page
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2002 Aug 21
9
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
maximum CDS input
voltage (peak-to-peak
value)
VCC = 2.85 V
650
−−
mV
VCC ≥ 3.0 V
800
−−
mV
Vreset(max)
maximum CDS input reset
pulse
−−
1.5
V
Ii(IN)
input current into pin IN
at floating gate level
−−
3
µA
Ci
input capacitance
2
pF
tCDS(min)
CDS control pulses
minimum active time
Vi(CDS)(p-p) = 800 mV;
black-to-white transition in
1 pixel with 98.5% Vi
recovery
11
−−
ns
th(IN;SHP)
CDS input hold time
(pin IN) compared to
control pulse SHP
Figs 3 and 4
3
−−
ns
th(IN;SHD)
CDS input hold time
(pin IN) compared to
control pulse SHD
Figs 3 and 4
3
−−
ns
Programmable Gain Amplifier (PGA)
DRPGA
PGA dynamic range
36
dB
∆GPGA
PGA gain step
0.08
0.10
0.12
dB
ADC
DNL
differential non linearity
ramp input
−±0.5
±0.9
LSB
ADCres
ADC resolution
10
bits
Total chain characteristics (CDS + PGA + ADC)
fpix(max)
maximum pixel rate
25
−−
MHz
fpix(min)
minimum pixel rate
OCCD(max) = ±100 mV
−−
1
MHz
OCCD(max) = ±200 mV
−−
2
MHz
OCCD(max)
maximum offset voltage
between CCD floating
level and CCD dark pixel
level
−200
+200
mV
tCLKH
CLK pulse width HIGH
15
−−
ns
tCLKL
CLK pulse width LOW
15
−−
ns
td(SHD;CLK)
time delay between
SHD and CLK
Figs 3 and 4
10
ns
tsu(BLK;SHD)
set-up time of BLK
compared to SHD
Figs 3 and 4
5
−−
ns
Vi(IN)
video input voltage for
ADC full-scale output
PGA code = 00
800
mV
PGA code = 383
12.7
mV
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT




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