поискавой системы для электроныых деталей |
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STW8019 датащи(PDF) 8 Page - STMicroelectronics |
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STW8019 датащи(HTML) 8 Page - STMicroelectronics |
8 / 55 page Ball/pin information STw8009/STw8019 8/55 3 Ball/pin information Table 1. Product name ball functions Ball Name Type Voltage Description E1 Vdd Power 1.2 V Digital core chip supply D2 Gndd GND 0 V Digital core chip ground C1 Vdd_IO1 Power 1.8 V Digital I/O supply D1 Vss_IO1 GND 0 V Digital I/O ground G4 Vdd_IO2 Power 1.8 V Digital I/O supply E4 Vss_IO2 GND 0 V Digital I/O ground A3 VccA1 Power 2.8 /3.3V DAC1 matrix analog power supply A5 VccA2 Power 2.8 /3.3 V DAC2 matrix analog power supply A7 VccA3 Power 2.8 /3.3 V 2.8/3.3 V digital feature supply B7 VccA4 Power 2.8 /3.3 V 2.8 /3.3 V digital feature supply B3 GNDA1 GND 0 V DAC1 ground B5 GNDA2 GND 0 V DAC2 ground C5 GNDA3 GND 0 V 2.8 /3.3 V digital feature ground B4 GNDA4 GND 0 V Rext ground connection B6 GNDA5 GND 0 V Analog ground A4 Rext Analog DAC current reference setting G2 CLK Digital Input 1.8 V 27 MHz master pixel clock (pixclk) G7, G6, F7, F6, E7, E6, D7, D6 YCbCr[0:7] Digital Input 1.8 V Time multiplexed 4:2:2 luminance and chrominance data as defined in CCIR 601 and CCIR 656 (excepted for TTL input signals) G5 Hsync Digital I/O 1.8 V Horizontal Synchronization signal: - Input in slave mode, except when sync is extracted from YcbCr data - Output in master mode and when sync is extracted from YcbCr signal. F5 Vsync Odd/Even Digital I/O 1.8 V Vertical Synchronization – Odd/Even signal: - Input in slave mode, except when sync is extracted from YcbCr data - Output in master mode and when sync is extracted from YcbCr signal. F3 SDA Digital I/O 1.8 V 2 wire serial MPU data line G3 SCL Digital Input 1.8 V 2 wire serial MPU clock E3 Add Digital input 1.8 V Device address selection C7 PORn Digital input 1.8 V Power On Reset (Active low) F2 Suspend Digital input 1.8 V Suspend input |
Аналогичный номер детали - STW8019 |
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Аналогичное описание - STW8019 |
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