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M40Z300AVMQ1F датащи(PDF) 6 Page - STMicroelectronics

номер детали M40Z300AVMQ1F
подробное описание детали  3V NVRAM Supervisor for Up to 8 LPSRAMs
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M40Z300AVMQ1F датащи(HTML) 6 Page - STMicroelectronics

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M40Z300AV
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OPERATION
The M40Z300AV, as shown in Figure 6., page 5,
can control up to four (eight, if placed in parallel)
standard low-power SRAMs. These SRAMs must
be configured to have the chip enable input dis-
able all other input signals. Most slow, low-power
SRAMs are configured like this, however many
fast SRAMs are not. During normal operating con-
ditions, the conditioned chip enable (E1CON to
E4CON) output pins follow the chip enable (E) input
pin with timing shown in Figure 7., page 6 and Ta-
ble 7., page 13. An internal switch connects VCC
to VOUT. This switch has a voltage drop of less
than 0.3V (IOUT1).
When VCC degrades during a power failure,
E1CON to E4CON are forced inactive independent
of E. In this situation, the SRAM is unconditionally
write protected as VCC falls below an out-of-toler-
ance threshold (VPFD). For the M40Z300AV, the
THS pin must be tied to ground (as shown in Table
6., page 11).
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time tWPT,
E1CON to E4CON are unconditionally driven high,
write protecting the SRAM. A power failure during
a WRITE cycle may corrupt data at the currently
addressed location, but does not jeopardize the
rest of the SRAM's contents. At voltages below
VPFD (min), the user can be assured the memory
will be write protected within the Write Protect
Time (tWPT) provided the VCC fall time exceeds tF
(see Figure 7., page 6).
As VCC continues to degrade, the internal switch
disconnects VCC and connects the internal battery
to VOUT. This occurs at the switchover voltage
(VSO). Below the VSO, the battery provides a volt-
age VOHB to the SRAM and can supply current
IOUT2 (see Table 6., page 11).
When VCC rises above VSO, VOUT is switched
back to the supply voltage. Outputs E1CON to
E4CON are held inactive for tCER (120ms maxi-
mum) after the power supply has reached VPFD,
independent of the E input, to allow for processor
stabilization (see Figure 11., page 12).
Two to Four Decode
The M40Z300AV includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in Table 2.
Table 2. Truth Table
Figure 7. Address-Decode Time
Note: During system design, compliance with the SRAM timing parameters must comprehend the propagation delay between E1CON -
E4CON.
Inputs
Outputs
E
BA
E1CON
E2CON
E3CON
E4CON
H
X
X
H
HHH
LLLL
H
H
H
LL
H
H
L
H
H
LHLH
HLH
L
HHH
HH
L
AI02551
A, B
E
E1CON - E4CON
tAS
tEDH
tEDL


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