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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C850 датащи(PDF) 11 Page - Advanced Micro Devices |
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AM79C850 датащи(HTML) 11 Page - Advanced Micro Devices |
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11 / 97 page  P R E L I M I N A R Y AMD 11 SUPERNET 3 PIN DESCRIPTION I/O pins can only be high impedance in Test Access Port (TAP) operation. Refer to TAP Testability section. PHY/PMD Interface (46 Pins) RX+, RX- Receive Data (PECL Input) These pins receive differential NRZI data. TX+, TX- Transmit Data (PECL Output) These transmit outputs carry differential NRZI data. They can be forced to logical 0 (TX+ LOW, TX- HIGH) by asserting the FOTOFF input. RCU Receive Control Upper (TTL input) RCU is asserted high to indicate that the upper nibble of the R bus (R7–4) is a network control character. When RCU is low, this nibble contains data. RCU is synchro- nous to BCLK. This pin has internal pull-up. RCL Receive Control Lower (TTL input) RCL is asserted high to indicate that the lower nibble of the R bus (R3–0) is a network control character. When RCL is low, this nibble contains data. RCL is synchro- nous to BCLK. This pin has internal pull-up. R7–0 Receive Bus (TTL input) The R bus is used to receive information from the external physical layer (PHY) device. Bytes clocked from the physical layer (PHY) into the SUPERNET 3 R-bus input are synchronous to the BCLK. These pins have internal pull-up. RPAR Receive parity (TTL input) RPAR is an input signal used to enhance error detection on the external PHY interface R7:0 bus. RPAR is an input signal used to implement even parity checking on R bus. If there is an odd number of 1’s on {R7:0, RCU, RCL}, then RPAR should be 1 and if there is an even number of 1’s on {R7:0, RCU, RCL} then RPAR should be 0. This pin has internal pull-up. RXAFU3–0 Receive Bus Tap for External AF (TTL output, high impedance) The internal MAC Receive bus lines upper nibble are tapped and brought out as the RXAFU 3–0 pins. These pins are used by an external AF to do external SA and/or DA match. RXAFL3–0 Receive Bus Tap for External AF (TTL output, TTL input, high impedance) The internal MAC Receive bus lines lower nibble are tapped and brought out as the RXAFL 3–0 pins. These pins are used by an external AF to do external SA and/or DA match. Note: The RXAFL[3:0] input pins are for diagnostic purposes only. RXAFCU Control Upper for AF Receive Bus (TTL output, high impedance) The RXAFCU output signal is used to flag control symbols being presented on the nibble (3:0) of the RXAFU bus. This signal is synchronous to BCLK. If RXAFCU is asserted high, the nibble on the RXAFU bus is interpreted as a network control character. Otherwise, it is interpreted as a data nibble. RXAFCL Control Lower for AF Receive Bus (TTL output, TTL input, high impedance) The RXAFCL output signal is used to flag control symbols being presented on the nibble (3:0) of the RXAFL bus. This signal is synchronous to BCLK. If RXAFCL is asserted high, the nibble on the RXAFL bus is interpreted as a network control character. Otherwise, it is interpreted as a data nibble. Note: The RXAFCL input is for diagnostic purposes only. X7–0 Transmit Bus (TTL output, high impedance) This eight-bit output bus is used to send control and data information to the external physical layer (PHY) device to be transmitted over the medium. Information on the X-bus output is synchronous to the BCLK. XPAR Transmit parity (TTL output, high impedance) XPAR is an output signal used to enhance error detection on the MAC—external PHY interface X7:0 bus. If there is an odd number of 1’s on {X7:0, XCU, XCL}, then XPAR should be 1 and if there is an even number of 1’s on {X7:0, XCU, XCL} then XPAR should be 0. XCU Transmit Control Upper (TTL output, high impedance) The XCU output signal is used to flag control symbols being presented on the upper nibble of the transmit bus. This signal is synchronous to BCLK. If XCU is asserted |
Аналогичный номер детали - AM79C850 |
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Аналогичное описание - AM79C850 |
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