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TSC8051C2XXX16CBR датащи(PDF) 4 Page - TEMIC Semiconductors

номер детали TSC8051C2XXX16CBR
подробное описание детали  8-Bit Microcontroller for Digital Computer Monitors
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производитель  TEMIC [TEMIC Semiconductors]
домашняя страница  http://www.temic.de
Logo TEMIC - TEMIC Semiconductors

TSC8051C2XXX16CBR датащи(HTML) 4 Page - TEMIC Semiconductors

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TSC8051C2
Rev. A (10 Jan. 97)
4
Preview
MATRA MHS
5. Pin Description
VSS
Circuit ground.
VCC
Power supply voltage.
RST
A high level on this pin for two machine cycles while the
oscillator is running resets the device. An internal
pulldown resistor permits power–on reset using only a
capacitor connected to VCC.
PORT 0 (P0.0–P0.7)
Port 0 is an 8–bit open–drain bidirectional I/O port. Port
0 pins that have 1’s written to them float, and in that state
can be used as high–impedance inputs.
Port 0 is also the multiplexed low–order address and data
bus during access to external Program and Data memory.
In this application it uses strong internal pull–up when
emitting 1’s.
Port 0 can sink and source 8 LS TTL loads.
PORT 1 (P1.0–P1.7)
Port 1 is an 8–bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL on
the data–sheet) because of the internal pullups.
Port 1 also serves 4 programmable PWM open drain
outputs and programmable open drain CPO, as listed
below:
Port Pin
Alternate Function
P1.0
PWM8: Pulse Width Modulation output 8.
P1.1
PWM9: Pulse Width Modulation output 9.
P1.2
PWM10: Pulse Width Modulation output 10.
P1.3
PWM11: Pulse Width Modulation output 11.
P1.4
CPO: Clamp Pulse Output.
Port 1 can sink and source 3 LS TTL loads.
PORT 2 (P2.0–P2.7)
Port 2 is an 8–bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL on
the data–sheet) because of the internal pullups.
Port 2 emits the high–order 8–bit address during fetches
from external Program Memory and during accesses to
external Data Memory that use 16–bit addresses. In this
application it uses strong internal pull–up when emitting
1’s.
Port 2 can sink and source 3 LS TTL loads.
PORT 3 (P3.0–P3.7)
Port 3 is an 8–bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IIL on
the data–sheet) because of the internal pullups.
Each line on this port has 2 or 3 functions either a general
I/O or special control signal, as listed below:
Port Pin
Alternate Function
P3.0
RXD: serial input port.
P3.1
TXD: serial output port.
P3.2
INT0: external interrupt 0.
VSYNC: vertical synchro input.
P3.3
INT1: external interrupt 1.
VOUT: buffered V-SYNC output.
P3.4
T0: Timer 0 external input.
HSYNC: horizontal synchro input.
P3.5
T1: Timer 1 external input.
HOUT: buffered H–SYNC output.
P3.6
WR: external data memory write strobe.
P3.7
RD: external data memory read strobe.
Port 3 can sink and source 3 LS TTL loads.
PWM0–7
These eight Pulse Width Modulation outputs are true
open drain outputs and are floating after reset.


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