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SN74AUCH16374ZQLR датащи(PDF) 2 Page - Texas Instruments |
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SN74AUCH16374ZQLR датащи(HTML) 2 Page - Texas Instruments |
2 / 12 page SN74AUCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES404D – JULY 2002 – REVISED MAY 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. terminal assignments 123456 A 1OE NC NC NC NC 1CLK B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 VCC VCC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 VCC VCC 2D6 2D5 J 2Q7 2Q8 GND GND 2D8 2D7 K 2OE NC NC NC NC 2CLK NC – No internal connection FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L ↑ H H L ↑ LL L H or L X Q0 H X X Z logic diagram (positive logic) 1OE 1CLK 1D1 To Seven Other Channels 1Q1 2OE 2CLK 2D1 2Q1 To Seven Other Channels 1 48 47 24 25 36 C1 1D 13 2 C1 1D Pin numbers shown are for the DGG and DGV packages. GQL PACKAGE (TOP VIEW) A B C D E F G H J K 1 2345 6 |
Аналогичный номер детали - SN74AUCH16374ZQLR |
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Аналогичное описание - SN74AUCH16374ZQLR |
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