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CAT24C03WI-G датащи(PDF) 8 Page - Catalyst Semiconductor |
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CAT24C03WI-G датащи(HTML) 8 Page - Catalyst Semiconductor |
8 / 20 page CAT24C03 8 Doc. No. 1113, Rev. A © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice READ OPERATIONS Immediate Address Read In standby mode, the CAT24C03 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that ‘previous’ byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. When, following a START, the CAT24C03 is presented with a Slave address containing a ‘1’ in the R/W bit position (Figure 8), it will acknowledge (ACK) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. The Master can stop further transmission by issuing a NoACK, followed by a STOP condition. Selective Read The Read operation can also be started at an address different from the one stored in the internal address coun- ter. The address counter can be initialized by performing a ‘dummy’ Write operation (Figure 9). Here the START is followed by the Slave address (with the R/W bit set to ‘0’) and the desired byte address. Instead of follow- ing up with data, the Master then issues a 2nd START, followed by the ‘Immediate Address Read’ sequence, as described earlier. Sequential Read If the Master acknowledges the 1st data byte transmitted by the CAT24C03, then the device will continue trans- mitting as long as each data byte is acknowledged by the Master (Figure 10). If the end of memory is reached during sequential Read, then the address counter will ‘wrap-around’to the beginning of memory, etc. Sequential Read works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address. |
Аналогичный номер детали - CAT24C03WI-G |
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Аналогичное описание - CAT24C03WI-G |
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