поискавой системы для электроныых деталей |
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ES29DL640FB-12RTG датащи(PDF) 9 Page - Excel Semiconductor Inc. |
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ES29DL640FB-12RTG датащи(HTML) 9 Page - Excel Semiconductor Inc. |
9 / 52 page ES I ES I 9 Rev.1C January 5, 2006 ES29LV400D Excel Semiconductor inc. In-System Unprotection “In-system unprotection”, the primary method, requires VID (11.5V~12.5V) on the RESET# with A6=1, A1=1, and A0=0. This method can be imple- mented either in-system or via programming equip- ment. This method uses standard microprocessor bus cycle timing. Refer to Fig. 26 for timing diagram and Fig. 3 for the unprotection algorithm. A9 High-Voltage Unprotection “High-voltage unprotection”, the alternate method intended only for programming equipment, must force VID (11.5~12.5V) on address pin A9 and con- trol pin OE# with A6=1, A1=1 and A0=0. Refer to Fig. 29 for timing diagram and Fig. 5 for the unpro- tection algorithm. Temporary Sector Unprotect This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID (11.5V-12.5V). During this mode, formerly protected sectors can be pro- grammed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are pro- tected again. Fig. 1 shows the algorithm, and Fig. 25 shows the timing diagrams for this feature. HARDWARE DATA PROTECTION The ES29LV400 device provides some protection measures against accidental erasure or program- ming caused by spurious system level signals that may exist during power transition. During power-up, all internal registers and latches in the device are cleared and the device automatically resets to the read mode. In addition, with its internal state machine built-in the device, any alteration of the memory contents or any initiation of new operation- can only occur after successful completion of spe- cific command sequences. And several features are incorporated to prevent inadvertent write cycles resulting from Vcc power-up and power-down transi- tion or system noise. Low Vcc Write inhibit When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc power-up and power-down. The command register and all internal program/ erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until Vcc is greater than VLKO. The system must provide proper signals to the control pins to prevent unin- tentional writes when Vcc is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical inhibit Write cycles are inhibited by holding any one of OE#=VIL, CE#=VIH or WE#=VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-up Write Inhibit If WE#=CE#=VIL and OE#=VIH during power up, the device does not accept any commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Notes: 1. All protected sectors are unprotected . 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) |
Аналогичный номер детали - ES29DL640FB-12RTG |
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Аналогичное описание - ES29DL640FB-12RTG |
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