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74ABT16899 датащит (PDF) 2 Page - NXP Semiconductors

№ деталь 74ABT16899
подробность  18-bit latched transceiver with 16-bit parity generator/checker 3-State
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
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74ABT16899 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74ABT16899
74ABTH16899
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
2
1998 Feb 25
853-1960 19018
FEATURES
Symmetrical (A and B bus functions are identical)
Selectable generate parity or ”feed-through” parity for A-to-B and
B-to-A directions
Independent transparent latches for A-to-B and B-to-A directions
Selectable ODD/EVEN parity
Continuously checks parity of both A bus and B bus latches as
ERRA and ERRB
Open-collector ERR output
Ability to simultaneously generate and check parity
Can simultaneously read/latch A and B bus data
Output capability: +64 mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power up 3-State
Power-up reset
Live insertion/extraction permitted
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with
separate transparent latches for the A bus and B bus. Either bus
can generate or check parity. The parity bit can be fed-through with
no change or the generated parity can be substituted with the SEL
input.
Parity error checking of the A and B bus latches is continuously
provided with ERRA and ERRB, even with both buses in 3-State.
The 74ABT/H16899 features independent latch enables for the A
and B bus latches, a select pin for ODD/EVEN parity, and separate
error signal output pins for checking parity.
FUNCTIONAL DESCRIPTION
The 74ABT/H16899 has three principal modes of operation which
are outlined below. All modes apply to both the A-to-B and B-to-A
directions.
Transparent latch, Generate parity, Check A and B bus parity:
Bus A (B) communicates to Bus B (A), parity is generated and
passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are
High and the Mode Select (SEL) is Low, the parity generated from
A0-A7 and B0-B7 can be checked and monitored by ERRA and
ERRB. (Fault detection on both input and output buses.)
Transparent latch, Feed-through parity, Check A and B bus
parity:
Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL
is High. Parity is still generated and checked as ERRA and ERRB
and can be used as an interrupt to signal a data/parity bit error to the
CPU.
Latched input, Generate/Feed-through parity, Check A (and B)
bus parity:
Independent latch enables (LEA and LEB) allow other permutations
of:
Transparent latch / 1 bus latched / both buses latched
Feed-through parity / generate parity
Check in bus parity / check out bus parity / check in and out bus
parity
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50pF; VCC = 5V
2.7
ns
tPLH
tPHL
Propagation delay
An to ERRA
CL = 50pF; VCC = 5V
5.0
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
CI/O
Output capacitance
Outputs disabled; VO = 0V or VCC
7
pF
ICCZ
Quiescent supply current
Outputs disabled; VCC =5.5V
500
µA
ICCL
Quiescent supply current
Output Low; VCC = 5.5V
10.5
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°C to +85°C
74ABT16899 DL
BT16899 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ABT16899 DGG
BT16899 DGG
SOT364-1
56-Pin Plastic SSOP Type III
–40
°C to +85°C
74ABTH16899 DL
BH16899 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ABTH16899 DGG
BH16899 DGG
SOT364-1


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