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GS8161E18BGT-200 датащи(PDF) 10 Page - GSI Technology

номер детали GS8161E18BGT-200
подробное описание детали  1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8161E18BGT-200 датащи(HTML) 10 Page - GSI Technology

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GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 9/2005
10/35
© 2004, GSI Technology
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00011011
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11000110
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00011011
2nd address
01
00
11
10
3rd address
10110001
4th address
11100100
Burst Counter Sequences
BPR 1999.05.18


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