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GS8180QV18D-200 датащи(PDF) 4 Page - GSI Technology

номер детали GS8180QV18D-200
подробное описание детали  18Mb Burst of 2 SigmaQuad SRAM
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8180QV18D-200 датащи(HTML) 4 Page - GSI Technology

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GS8180QV18/36D-200/167/133/100*
Rev: 2.03 10/2004
4/32
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate
I/O SRAM that shares a common address between its two ports to keep both ports running all the time, the RAM must implement
some sort of burst transfer protocol. The burst must be at least long enough to cover the time the opposite port is receiving
instructions on what to do next. The rate at which a RAM can accept a new random address is the most fundamental performance
metric for the RAM. Each of the three SigmaQuad SRAMs support similar address rates because random address rate is
determined by the internal performance of the RAM and they are all based on the same internal circuits. Differences between the
truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from differences in how the RAM’s
Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
NC
No Connect
R
Synchronous Read
Input
Active Low
W
Synchronous Write
Input
Active Low
BW0–BW1
Synchronous Byte Writes
Input
Active Low
K
Input Clock
Input
Active High
K
Input Clock
Input
Active Low
C
Output Clock
Input
Active High
C
Output Clock
Input
Active Low
TMS
Test Mode Select
Input
TDI
Test Data Input
Input
TCK
Test Clock Input
Input
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input
ZQ
Output Impedance Matching Input
Input
MCL
Must Connect Low
D0–D17
Synchronous Data Inputs
Input
Q0–Q17
Synchronous Data Outputs
Output
VDD
Power Supply
Supply
2.5 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
VSS
Power Supply: Ground
Supply


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