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GS8330LW36C-200 датащи(PDF) 9 Page - GSI Technology

номер детали GS8330LW36C-200
подробное описание детали  36Mb 誇1x1Lp CMOS I/O Late Write SigmaRAM
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8330LW36C-200 датащи(HTML) 9 Page - GSI Technology

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Rev: 1.00 6/2003
9/30
© 2003, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8330LW36/72C-250/200
SigmaRAM Late Write SRAM Burst Writes with Counter Wrap-around
Burst Order
The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have
been accessed. SigmaRAMs always count in linear burst order.
Linear Burst Order
Note: The burst counter wraps to initial state on the 5th rising edge of clock.
Echo Clock
SRAMs feature Echo Clocks, CQ1, CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
D1
D2
XX
XX
A2
Counter Wraps
Continue
/E1
ADV
DQ
D2
ADV
Continue
CK
Address
A2
XXXXXX
Continue
Continue
Write
D0
/W
A1
A2
A3
A0
D3
Internal
Addres


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