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GS8321Z18GE-200V датащи(PDF) 1 Page - GSI Technology |
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GS8321Z18GE-200V датащи(HTML) 1 Page - GSI Technology |
1 / 32 page Rev: 1.05 6/2006 1/32 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321Z18/32/36E-xxxV 36Mb Pipelined and Flow Through Synchronous NBT SRAM 250 MHz–133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O 165-Bump FP-BGA Commercial Temp Industrial Temp Features • User-configurable Pipeline and Flow Through mode • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization • Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • IEEE 1149.1 JTAG-compatible Boundary Scan • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply • LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • ZZ pin for automatic power-down • JEDEC-standard 165-bump FP-BGA package • RoHS-compliant 165-bump BGA package available Functional Description The GS8321Z18/32/36E-xxxV is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8321Z18/32/36E-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge- triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8321Z18/32/36E-xxxV is implemented with GSI's high performance CMOS technology and is available in JEDEC- standard 165-bump FP-BGA package. Parameter Synopsis -250 -225 -200 -166 -150 -133 Unit Pipeline 3-1-1-1 tKQ tCycle 3.0 4.0 3.0 4.4 3.0 5.0 3.5 6.0 3.8 6.6 4.0 7.5 ns ns Curr (x18) Curr (x32/x36) 285 350 265 320 245 295 220 260 210 240 185 215 mA mA Flow Through 2-1-1-1 tKQ tCycle 6.5 6.5 7.0 7.0 7.5 7.5 8.0 8.0 8.5 8.5 8.5 8.5 ns ns Curr (x18) Curr (x32/x36) 205 235 195 225 185 210 175 200 165 190 155 175 mA mA |
Аналогичный номер детали - GS8321Z18GE-200V |
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Аналогичное описание - GS8321Z18GE-200V |
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