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GS8342Q36GE-300 датащи(PDF) 8 Page - GSI Technology

номер детали GS8342Q36GE-300
подробное описание детали  36Mb SigmaQuad-II Burst of 4 SRAM
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8342Q36GE-300 датащи(HTML) 8 Page - GSI Technology

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Preliminary
GS8342Q08/09/18/36E-300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 8/2005
8/34
© 2003, GSI Technology
SigmaQuad-II B2 SRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of
K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is
clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on
the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.
SigmaQuad-II B2 Double Data Rate SRAM Write First
Write A
Read B
Read C Write D
NOP
Read E Write F
Read G Write H
NOP
A
B
C
D
E
F
G
H
A
A+1
D
D+1
F
F+1
H
H+1
A
A+1
D
D+1
F
F+1
H
H+1
B
B+1
C
C+1
E
E+1
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
SigmaQuad-II B4 SRAM DDR Read
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NBx” may be substituted in all the discussion above.


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