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74ALS563AN датащи(PDF) 2 Page - NXP Semiconductors |
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74ALS563AN датащи(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74ALS563A/74ALS564A Latch/flip-flop 74ALS563A Octal transparent latch, inverting (3-State) 74ALS564A Octal D flip-flop, inverting (3-State) 2 1996 Jul 01 853–1306 01670 FEATURES • 74ALS563A is broadside pinout and inverting version of 74ALS373 • 74ALS564A is broadside pinout and inverting version of 74ALS374 • Inputs and outputs on opposite side of package allow easy interface to microprocessors • Useful as an input or output port for microprocessors • 3-State outputs for bus interfacing • Common output enable • 74ALS573A and 74ALS574A are non-inverting version of 74ALS563B and 74ALS564A respectively TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74ALS563A 6.0ns 12mA 74ALS564A 6.0ns 15mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 20-pin plastic DIP 74ALS563AN, 74ALS564AN SOT146-1 20-pin plastic SOL 74ALS563AD, 74ALS564AD SOT163-1 DESCRIPTION The 74ALS563A is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The 74ALS563A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the inverted data that is present one setup time before the High-to-Low enable transition. The 74ALS564A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. It is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates. The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. The active-Low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, latched or transparent data appears at the output. When OE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 – D7 Data inputs 1.0/2.0 20 µA/0.2mA E (74ALS563A) Enable input 1.0/1.0 20 µA/0.1mA OE Output enable input (active-Low) 1.0/1.0 20 µA/0.1mA CP (74ALS564A) Clock pulse input (active rising edge) 1.0/2.0 20 µA/0.2mA Q0 – Q7 Data outputs 130/240 2.6mA/24mA NOTE: One (1.0) ALS unit load is defined as: 20 µA in the High state and 0.1mA in the Low state. |
Аналогичный номер детали - 74ALS563AN |
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Аналогичное описание - 74ALS563AN |
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