SL811S/T
Document #: 38-08009 Rev. **
Page 6 of 27
4.2
Block Diagram
4.3
Features
4.3.1
USB Specification Compliance
• Conforms to USB Specification 1.1
4.3.2
CPU Interface
• Standard Microprocessor Interface
• Supports DMA Transfers
• 256 x 8 SRAM “On-Chip” memory
• 8-bit Bidirectional Data Port, interfaces to any external Bus or CPU (Intel, Motorola, etc.)
• Four USB Endpoints
• On-Chip USB transceivers
• On-Chip full/slow speed USB transceivers
• Supports power suspend mode
• 3.3V power source, CMOS Technology
• Logic interface is 5 Volt tolerant
• Memory buffer includes Double buffer Ping Pong operation scheme
• Operates on either 12-MHz or 48-MHz crystal/clock.
• Auto Address increment mode to simplify memory access and improve performance
• Available in 28-Pin PLCC or 48 LPQFP packages
• Generic WDM Mini Port driver for Windows 98, 2000/NT 5.0, and CE3.0, firmware and system USB demo source examples
are available.
4.4
Data Port, Interface to external Micro-Processor
The SL811S/T Data Port interface provides an 8-bit bidirectional data path with appropriate control signals such as CS, RD, WR,
A0 and INTR lines. This feature enables it to interface to any external processor or controller (Intel, Motorola, TI, Analog Devices,
etc.). The control Read and Write signals, Chip Select and a single address line A0, with the 8-bit data bus, support both
programmed I/O or Memory mapped I/O designs.
Access to the memory and control register space is a simple two step process, requiring an address write with A0 set to '0' followed
by a register/memory read or write cycle with address line A0 set to '1'.
X1
X2
D+
D-
INTR
nDRQ
nDACK
nWR
nRD
nCS
nRST
D0-D7
GENERATOR
USB
XCVRS
SERIAL
INTERFACE
ENGINE
RAM
BUFFER
CONTROL
REGISTERS
INTERRUPT
INTERFACE
CLOCK
&
CONTROLLER
DMA
PROCESSOR
INTERFACE
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
