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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM85C30-16BUA датащи(PDF) 9 Page - Advanced Micro Devices |
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AM85C30-16BUA датащи(HTML) 9 Page - Advanced Micro Devices |
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9 / 68 page  AMD 9 Am85C30 ARCHITECTURE The ESCC internal structure includes two full-duplex channels, two 10 × 19 bit SDLC/HDLC frame status FIFOs, two baud rate generators, internal control and in- terrupt logic, and a bus interface to a non-multiplexed bus. Associated with each channel are a number of Read and Write registers for mode control and status in- formation, as well as logic necessary to interface with modems or other external devices (see Logic Symbol). The logic for both channels provides formats, synchroni- zation, and validation for data transferred to and from the channel interface. The modem control inputs are monitored by the control logic under program control. All of the modem control signals are general-purpose in na- ture and can optionally be used for functions other than modem control. The register set for each channel includes ten control (Write) registers, two SYNC character (Write) registers, and four status (Read) registers. In addition, each baud rate generator has two (Read/Write) registers for hold- ing the time constant that determines the baud rate. Fi- nally, associated with the interrupt logic is a Write register for the interrupt vector accessible through either channel, a Write-only Master Interrupt Control register, and three Read registers: one containing the vector with status information (Channel B only), one containing the vector without status (A only), and one containing the in- terrupt pending bits (A only). The registers for each channel are designated as follows: WR0–WR15—Write Registers 0 through 15. An addi- tional Write register, WR7 Prime (WR7 ′), is available for enabling or disabling additional SDLC/HDLC enhance- ments if bit D0 of WR15 is set. RR0–RR3, RR10, RR12, RR13, RR15—Read Regis- ters 0 through 3, 10, 12, 13, and 15. If bit D2 of WR15 is set, then two additional Read regis- ters, RR6 and RR7, are available. These registers are used with the 10 × 19 bit Frame Status FIFO. Table 1 lists the functions assigned to each Read and Write register. The ESCC contains only one WR2 and WR9, but they can be accessed by either channel. All other registers are paired (one for each channel). Channel B Registers Data Control CPU Bus VO Internal Control Logic Internal Bus Channel A Registers Interrupt Control Logic +5 V GND PCLK Channel A Channel B Control Logic Transmitter Receiver Baud Rate Generator 10 ×19 Bit Frame Status FIFO Interrupt Control Lines TxDA RxDA RTxCA TRxCA SYNCA RTSA CTSA DCDA RxDB RTxCB TRxCB SYNCB RTSB CTSB DCDB 5 10216F-5 TxDB 8 Figure 1. Block Diagram of ESCC Architecture |
Аналогичный номер детали - AM85C30-16BUA |
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Аналогичное описание - AM85C30-16BUA |
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