December 1990

2

Philips Semiconductors

Product specification

8-bit shift register with input latches

74HC/HCT7597

FEATURES

• 8-bit parallel input latches

• Shift register has direct overriding load and clear

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT7597 are high-speed Si-gate CMOS

devices and are pin compatible with low power Schottky

TTL (LSTTL). They are specified in compliance with

JEDEC standard no. 7A.

The 74HC/HCT7597 both consist of an 8-bit storage latch

feeding a parallel-in, serial-out 8-bit shift register.

In this condition the latches are transparent, i.e. a latch

output will change state each time its corresponding

D-input changes.

When LE is HIGH the latches store the information that

was present at the D-inputs, a set-up time preceding the

LOW-to-HIGH transition of LE.

The shift register has a positive edge-triggered clock,

direct load (from storage) and clear inputs.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

15

17

ns

LE to Q

22

27

ns

PL to Q

20

23

ns

20

24

ns

99

79

MHz

input capacitance

3.5

3.5

pF

power dissipation capacitance per package

notes 1, 2

29

30

pF