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74LVC646ADB датащи(PDF) 2 Page - NXP Semiconductors |
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74LVC646ADB датащи(HTML) 2 Page - NXP Semiconductors |
2 / 16 page Philips Semiconductors Product specification 74LVC646A Octal bus transceiver/register (3-State) 2 1998 Jul 29 853-2105 19803 FEATURES • Wide supply voltage range of 1.2V to 3.6V • Flow-through pin-out architecture • In accordance with JEDEC standard no. 8-1A • CMOS low power consumption • Direct interface with TTL levels • 5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic DESCRIPTION The 74LVC646A is a high performance, low-power, low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC646A consist of non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the ‘A’ or ‘B’ register, or in both. The select source inputs (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The direction (DIR) input determines which bus will receive data when OE is active (LOW). In the isolation mode (OE = HIGH), ‘A’ data may be stored in the ‘B’ register and/or ‘B’ data may be stored in the ‘A’ register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, ‘A’ or ‘B’ may be driven at a time. The ‘646A’ is functionally identical to the ‘648A’ but has non-inverting data paths. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay An to Yn CL = 50pF VCC = 3.3V 3.9 ns fmax Maximum clock frequency 250 MHz CI Input capacitance 5.0 pF CI/O Input/output capacitance 10 pF CPD Power dissipation capacitance per gate Notes 1, 2 26 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi )Σ (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING AND PACKAGE INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 24-Pin Plastic SO –40 °C to +85°C 74LVC646A D 74LVC646A D SOT137-1 24-Pin Plastic SSOP Type II –40 °C to +85°C 74LVC646A DB 74LVC646A DB SOT340-1 24-Pin Plastic TSSOP Type I –40 °C to +85°C 74LVC646A PW 7LVC646APW DH SOT355-1 |
Аналогичный номер детали - 74LVC646ADB |
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Аналогичное описание - 74LVC646ADB |
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