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74LVC652PW датащи(PDF) 2 Page - NXP Semiconductors |
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74LVC652PW датащи(HTML) 2 Page - NXP Semiconductors |
2 / 14 page Philips Semiconductors Product specification 74LVC652 Octal transceiver/register with dual enable (3-State) 2 1998 Jul 29 853-2104 19803 *FEATURES • Wide supply voltage range of 1.2V to 3.6V • In accordance with JEDEC standard no. 8-1A • CMOS low power consumption • Direct interface with TTL levels • 5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic DESCRIPTION The 74LVC652 is a high performance, low-power, low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC652 consist of 8 non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the ‘A’ or ‘B’ or both buses, will be stored in the internal registers, at the appropriate clock inputs (CPAB or CPBA) regardless of the select inputs (SAB and SBA) or output enable (OEAB and OEBA) control inputs. Depending on the select inputs SAB and SBA data can directly go from input to output (real time mode) or data can be controlled by the clock (storage mode), this is when the OEn inputs this operating mode permits. The output enable inputs OEAB and OEBA determine the operation mode of the transceiver. When OEAB is LOW, no data transmission from An to Bn is possible and when OEBA is HIGH, there is no data transmission from Bn to An possible. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each output reinforces its input. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay An to Bn; Bn to An CL = 50pF VCC = 3.3V 5.0 ns fmax Maximum clock frequency 150 MHz CI Input capacitance 5.0 pF CPD Power dissipation capacitance per latch Notes 1, 2 45 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 x fi )Σ (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING AND PACKAGE INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 24-Pin Plastic SO –40 °C to +85°C 74LVC652 D 74LVC652 D SOT137-1 24-Pin Plastic SSOP Type II –40 °C to +85°C 74LVC652 DB 74LVC652 DB SOT340-1 24-Pin Plastic TSSOP Type I –40 °C to +85°C 74LVC652 PW 4LVC652PW DH SOT355-1 |
Аналогичный номер детали - 74LVC652PW |
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Аналогичное описание - 74LVC652PW |
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